The subject system and method are generally directed to memory controllers for controlling highly reliable access to memory devices for data words stored with both data bits and associated error checking bits. The system and method include measures for preserving the integrity of address bits corresponding to the data words that are to be read and/or written in connection with a given memory transaction. In certain embodiments and applications, the subject system and method accomplish this by productively exploiting the capabilities of a memory controller executable to dynamically adapt memory transactions involving such error-protected data words in accordance with an inline memory storage paradigm.
More specifically, the subject system and method make use of the built-in redundancy of address bit checking inherent to such memory controller's use of adaptively split addressing for the data and error checking components of data words. The subject method and system supplement this inherent capability to preserve address protection through the full address path, effectively from where the memory controller receives a memory transaction through its interface ports to where it executes the memory transaction through its split-address processing for memory device access.
Memory controllers are well known in the art. They are implemented as digital circuits dedicated to controlling/managing the flow of data written to and read from one or more memory devices. They may be suitably formed as separate devices or integrated with a central processing unit or other main controller, and serve the memory storage and access needs of various control or user application ‘master’ operations processed thereby. Memory controllers implement the logic necessary to read from and write to various types of memory devices, examples of which include dynamic random access memory (DRAM), as well as electrically programmable types of non-volatile memory such as flash memory, and the like.
To minimize the consequences of data corruption due to random sources of error, various error checking measures for detection and/or correction are employed in the art for the storage and retrieval of data from memory devices. One example of the various known measures is the use of an Error Correcting Code (ECC) for detection and/or correction of error in data words. ECC measures are widely implemented in memory controllers heretofore known in various computer applications that may be particularly vulnerable to data corruption, or more generally in high data rate or other such applications where substantial immunity to data corruption is particularly important, and the added processing burden and complexity of ECC are not prohibitive. ECC measures generally involve adding redundant ECC bits to a transmitted data segment according to a predetermined code (of selected ECC format). These ECC bits are of parity-type, and permit the data segment to be properly recovered at the receiving end (by a receiving/recovery measures suitably configured for the given ECC format), even if certain correctable errors were introduced in the transmission or storage of that data segment. The degree to which the errors are correctable would depend on the relevant properties of the particular code being used.
In addition to the need to guard against corruption of the data bits carrying the substantive information involved in memory transactions, there is corresponding need to guard against corruption of the address bits identifying the memory storage locations of those data bits. After all, data bits properly read from or written to an incorrect location are just as corruptive as data bits improperly read from or written to a correct location. Yet, the integrity of the address bits for data bits involved in memory transactions are typically not as safely guarded as the data bits themselves.
Known memory controllers are widely configured for storage of such ECC-protected data according to the so-called sideband ECC storage format. They generally transmit, receive, and store data words. With increasing data speed and memory capacities, data word formats have grown to be defined by numerous multi-bit bytes. In typical ECC-protected memory controller applications, for example, a data word may be defined by 72 total bits, segmented into eight 8-bit data bytes and one 8-bit ECC byte (or one ECC bit for each 8-bit data byte). The multiple data bytes of each data word are often stored for high capacity applications in a memory device formed by a plurality of integrated circuit chips. Each data byte in those applications is stored in a different selectable chip, though at the same relative address within each chip. Sideband storage of ECC and data bits provides for an additional chip in which to store the ECC byte associated with the given data word's data bytes. The data word's ECC byte is then stored much like its data bytes—at the same intra-chip address as those data bytes, but in its designated sideband ECC chip(s). So in the case of a 72-bit data word (formed by 8 data bytes plus 1 ECC byte), for example, the data word is stored across nine selectable chips, eight for the data bytes and one for the associated ECC byte.
Memory transactions for reading and writing data to/from memory initiated by master control operations in many applications contemplate such sideband storage of ECC bytes with their associated data bytes. But a memory device sufficiently equipped to support sideband storage may not be available in certain applications, though the need for ECC protection for memory transactions remains. This may be due to various reasons in practice, reasons such as: form factor limitations, cost constraints, prohibitive memory technology, or the like. The memory controller system disclosed herein provides for dynamically adapting a memory transaction for inline storage configurations, where different portions of given data words are stored at different intra-chip addresses with split addressing for
data and ECC bytes. The split addressing provides a built-in check against address corruption since a corruption in either of the addresses for data and ECC bytes will become apparent when ECC check is made therefor. But such protection against address corruption does not reach beyond those portions of the memory controller system outside the split addressed processing. There is therefore a need for suitable measures to extend address protection for the data words of memory transactions carried out by a memory controller system through the entire address path, including those portions of the path outside the split addressed processing carried out for inline storage of corresponding data and error-checking bytes.